Data Cache Management
Writing device drivers for processors with a data cache is a fairly tricky process. If the network hardware accesses memory via DMA, all outgoing packets must be flushed from the cache to main memory, and all received packets must be stored into buffers that are not currently cached (that is, have been invalidated in the cache). Adding to the difficulty is the fact that any buffer which might need to be invalidated must begin and end on cache line boundaries, to avoid incorrectly invalidating adjacent memory areas.
Data Buffer Alignment
TM_PACKET_BUF_CACHE_ALIGN must be defined in <trsystem.h> to the cache line size of the data cache. When this macro is set, the stack will allocate all packet buffers such that they begin and end on cache line boundaries. This makes it possible to invalidate an entire packet buffer without invalidating nearby memory that isn't part of the packet.
Enabling Data Cache Management
To enable data cache management, define TM_USE_DCACHE_MANAGEMENT in <trsystem.h>. This allows the stack to automatically handle flushing and invalidation of packet buffers. This functionality does not work on byte-stuffing interfaces (e.g., PPP and SLIP). Defining this macro makes three data cache management APIs available.
Data Cache Management APIs
Modifications to Treck Device Driver Buffer Pool APIs
The device driver buffer pool has been modified to make use of the "cache-safe" functionality discussed above. Specifically, when refilling the pool on an interface that has a "cache invalidate" function available, newly allocated buffers will be invalidated before being given to the driver to be used.